1. Field of the Invention
The present invention relates to a method for forming a conductive structure, and more particularly to a method for forming a conductive structure which has, in its interior, via plugs vertically penetrating the structure and, in its surface, electrode pads and/or a rewiring structure connecting to the via plugs, and which can be used in three-dimensional packaging of semiconductor chips utilizing the via plugs.
The present invention also relates to a plating apparatus and a plating method which are useful for filling a metal into via holes in the manufacturing of an interposer or spacer which has a number of via plugs vertically penetrating in its interior, and which can be used in so-called three-dimensional packaging of semiconductor chips.
2. Description of the Related Art
A three-dimensional packaging technology, which involves laminating a plurality of semiconductor chips into a multi-layer package, is attracting attention especially as a technique for achieving higher-density LSI packaging in order to provide smaller-sized and higher-performance electronic products. A wire bonding method for laminating semiconductor chips has already been put into practical use and is currently used, e.g., in packaging for flash memory products, to provide high-capacity products. The wire bonding method, however, has the drawback that wires for connecting electrodes have a length of a millimeter level, which is materially longer that the length of interconnects of a chip. Therefore problems, such as signal delay, would arise when wire bonding is employed in packaging for devices that treat high-speed signals, such as DRAMs and logic devices. A study is therefore being conducted on a three-dimensional packaging technology using via plugs, which involves forming via plugs of a conductive material, such as copper, in a substrate and connecting semiconductor chips with the via plugs by the most direct way, thereby making it possible to provide smaller-sized and higher-performance electronic products.
Semiconductor chips cannot be connected to each other merely by providing via plugs in a substrate. Thus, it is necessary to form electrode pads directly on the via plugs in the surface of the substrate, or to form a rewiring layer for rearrangement of the positions of the electrode pads. It is also conceivable to form a lead-free solder bonding layer on the electrode pads.
FIGS. 1A through 2C illustrate a process for the production of a conductive structure comprising a substrate and having, in an interior of the substrate, via plugs of copper vertically penetrating the substrate, and having, in a surface of the substrate, electrode pads of copper. First, as shown in FIG. 1A, a substrate W having a plurality of upwardly-open via holes (recesses for via plugs) 12, formed by the lithography/etching technique or the like in a base 10 of, e.g., silicon, is provided, and a seed layer (conductive film) 14 of, e.g., copper, which serves as a feeding layer upon electroplating, is formed by sputtering or the like on an entire surface, including interior surfaces of the via holes 12, of the substrate W.
Copper electroplating is carried out on the surface of the substrate W to deposit a first plated film 16 on a surface of the seed layer 14 while filling the via holes 12 with the first plated film 16, as shown in FIG. 1B. Thereafter, the extra first plated film 16, lying outside the via holes 12, is polished away by chemical mechanical polishing (CMP) or the like, as shown in FIG. 1C.
Next, as shown in FIG. 2A, a resist pattern 18 is formed, e.g., with a photoresist at a predetermined position on the surface of the substrate W in such a manner that the positions and the shapes of resist openings 20 correspond to electrode pads to be formed. Thereafter, copper electroplating is carried out on the surface of the substrate W to form a second plated film 22 in the resist openings 20 of the resist pattern 18, as shown in FIG. 2B. Thereafter, as shown in FIG. 2C, the extra seed layer 14 and the resist pattern 18 are removed from the surface (front surface) of the substrate W and, at the same time, the back surface of the substrate W is polished and removed until the bottom of the first plated film 16 embedded in the via holes 12 becomes exposed, thereby obtaining a conductive structure having via plugs 24 of copper, composed of the first plated film 16 embedded in the via holes 12, and having electrode pads 26 composed of the second plated film 22 which has been formed in the resist openings 20 of the resist pattern 18.
FIGS. 3A through 3D illustrate a process for the production of an interposer or a spacer having, in its interior, a plurality of copper via plugs which, when laminating semiconductor substrates in multiple layers, electrically connect the layers. First, as shown in FIG. 3A, a substrate W is provided which has been prepared by depositing an insulating film 512 of, e.g., SiO2 on a surface of a base 510 of, e.g., silicon, and then forming a plurality of upwardly-open via holes 514 by the lithography/etching technique or the like. The diameter “d” of the via holes 514 is, for example, 1 μm to 100 μm, in particular 10 μm to 20 μm, and the depth “h” is, for example, 70 μm to 150 μm. A barrier layer 516 of, e.g., TaN is formed on a surface of the substrate W and then a (copper) seed layer 518, which serves as a feeding layer upon electroplating, is formed on a surface of the barrier layer 516 by sputtering or the like, as shown in FIG. 3B.
Thereafter, copper electroplating is carried out on the surface of the substrate W to deposit a copper plated film 520 over the insulating film 512 while filling the via holes 514 with copper (plated film), as shown in FIG. 3C.
Thereafter, as shown in FIG. 3D, the extra copper film 520, the seed layer 518 and the barrier layer 516 on the insulating film 512 are removed by chemical mechanical polishing (CMP) or the like and, at the same time, the back surface of the substrate W is polished and removed until the bottom surface of the copper embedded in the via holes 514 becomes exposed, thereby obtaining an interposer or a spacer having via plugs 522 of copper vertically penetrating in its interior.
In order to securely fill a metal film into such deep high-aspect ratio via holes, generally having a diameter of 1 μm to 100 μm, in particular 10 to 20 μm, and a depth of 70 μm to 150 μm, formed in a substrate, while preventing the formation of defects such as voids in the embedded metal film, the applicant has proposed a plating apparatus which changes a voltage, applied from a plating power source to between a substrate and an anode, in the course of plating (see Japanese Patent Laid-Open Publication No. 2005-97732) and a plating apparatus which carries out stirring of a plating solution when no voltage is applied between a substrate and an anode, and stops stirring of the plating solution when a voltage is applied between the substrate and the anode (see Japanese Patent Laid-Open Publication No. 2006-152415).
The use of electroplating for the formation of via plugs is being studied, as described above. In order to form via plugs by electroplating, it is necessary to form, in advance of plating, via holes (recesses for via plugs) having a diameter of the order of several to 100 μm and a depth of the order of several tens to several hundred μm, and to fill a plated film of, e.g., copper into the via holes. However, it takes a considerably long time to fill a defect-free plated film into such large via holes by a common electroplating method. The low productivity poses an impediment to the practical use of electroplating in the formation of via plugs. When forming a conductive structure by the process shown in FIGS. 1A through 2C, the process must pass through the number of steps of: plating→CMP→resist formation→plating. This process thus involves a high production cost. It may therefore be considered to form electrode pads, a rewiring layer, and also a bonding solder layer directly on via plugs successively by electroplating. However, because these layers each have a thickness of not less than several μm, it will take a further long time to form the via plugs and the layers successively by electroplating under the same plating conditions.
Further, it has been found that in the plating apparatuses described in the above-cited patent documents, a plated film is formed in excess also in a surface area of a substrate other than via holes, and that because of no countermeasure taken for reducing a thickness of the plated film formed on that surface area, the polishing amount in a later CMP process is large and the production cost is high. This poses an impediment to the practical use of the plating apparatuses. In particular, as shown in FIG. 4, when plating of a substrate surface is carried out to fill holes having a diameter of D1 with a plated film, a plated film having a thickness of T1 is formed also on the substrate surface outside the holes. The thickness T1 will be not less than ½ of the hole diameter D1 (T1>D1/2). Therefore, in order to reduce a burden on a later CMP process, it is desirable that the formation of a copper film by plating be performed selectively in via holes with little formation of the copper film in the other area.
It is noted in this regard that when filling via holes of a substrate with a metal copper by plating, if the rates of the growth of plating inside and outside the via holes are equal, a thickness of a plated film, which is the same as the radius of the via holes, is needed. If no countermeasure is taken, a plated film having the same thickness will be formed also in the surface area, other than the via holes, of the substrate. Though the growth of plating can be suppressed to some extent, e.g., by the use of an additive in a plating solution, it is not enough.